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[Windows Developram

Description: verilog写双端口存储器模型-a Model of Writing Double-Port RAM developed with Verilog
Platform: | Size: 1024 | Author: 杨艳 | Hits:

[VHDL-FPGA-Verilogverilog实例

Description: 一些很实用的verilog源程序,是初学者的好棒手,希望能给需要的人一点帮助,请支持一下。-some very practical Verilog source is the beginners excellent hands, in hopes of giving those who need a bit of help, please support what.
Platform: | Size: 165888 | Author: 叶若寒 | Hits:

[CommunicationDDS_VERILOG

Description: 本例给出了DDS的VERIOG的程序事例,可发生正弦\余弦等波形,适应与通信方面的硬件实现!-the cases presented DDS VERIOG procedures example, can occur sine \ cosine wave such as, Adaptation and communications hardware realization!
Platform: | Size: 3072 | Author: 陈榧 | Hits:

[VHDL-FPGA-VerilogDDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波,方波,三角波,斜波,以及四种波形的任意两种的叠加,以及四种波形的叠加;通过控制频率控制字C的大小,以控制输出波形频率,实现1Hz的微调;通过地址变换实现波形相位256级可调;通过DAC0832使波形幅值256级可调;通过FPGA内部RAM实现波形存储回放;并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16384 | Author: 田世坤 | Hits:

[VHDL-FPGA-VerilogAD9852

Description: 数字频率合成器芯片AD9852 的配置文件,HDL级的Verilog代码-DDS chip AD9852 profile, HDL-level Verilog code
Platform: | Size: 1024 | Author: 李春阳 | Hits:

[VHDL-FPGA-Verilogsine

Description: Verilog编程,利用FPGA实现两路正弦波的信号输出,也可以扩展成六路正弦输出-Verilog programming, the use of FPGA realize two sinusoidal output signals can also be extended into a six-way sinusoidal output
Platform: | Size: 4792320 | Author: 陈剑 | Hits:

[Software EngineeringDDS

Description: 基于DDS原理的正弦信号发生器。用VERILOG语言实现,功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
Platform: | Size: 558080 | Author: 毛华站 | Hits:

[VHDL-FPGA-Verilogaccumulator

Description: 实现累加器的verilog源码,广泛应用在通信电路设计中-The realization of accumulator Verilog source, widely used in communication circuit design
Platform: | Size: 1024 | Author: 文明 | Hits:

[Graph Drawingdds(heli)

Description: DDS用verilog 实现,可以实现方波、正弦和三角-DDS using verilog realized, can be square wave, sinusoidal and triangular
Platform: | Size: 428032 | Author: qian | Hits:

[VHDL-FPGA-VerilogDDS

Description: 同时用verilog 语言编写dds原代码用于生成正余弦波,并在FPGA平台进行验证-described dds direct digital frequency synthesis of the basic tenets addition to the use of verilog prepared dds source used to produce sine, and FPGA development platform for verification
Platform: | Size: 1024 | Author: scond | Hits:

[VHDL-FPGA-VerilogCORDIC_SINE

Description: xilinx的ISE工程,用CORDIC算法做DDS生成正弦波-xilinx the ISE project to do with the CORDIC algorithm generates sine DDS
Platform: | Size: 14447616 | Author: 刘伟 | Hits:

[VHDL-FPGA-VerilogAD9954_test

Description: AD公司DDS芯片AD9954的Verilog测试程序-VerilogHDL test program of DDS chip--AD9954 ,producted by AD company
Platform: | Size: 2068480 | Author: ch | Hits:

[VHDL-FPGA-Verilogdds

Description: verilog 硬件语言实现DDS,使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
Platform: | Size: 2594816 | Author: linzi | Hits:

[VHDL-FPGA-VerilogDDS

Description: DDS数字频率合成的verilog代码,附有正余弦查找表等-DDS digital frequency synthesis verilog code, with a cosine look-up table, etc.
Platform: | Size: 16772096 | Author: allen-haha | Hits:

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